1. Field of the Invention
The present invention generally relates to electron beam (e-beam) lithography and, more particularly, to the development of control signals for producing an exposure pattern with an electron beam lithography tool.
2. Description of the Prior Art
The patterning of layers of conductors, semiconductor material and insulators on substrates or other deposited layers is essential to the formation of many electronic components and is well known in the electronics industry. The formation of integrated circuits is almost entirely reliant on methods of achieving such patterns of materials and many sophisticated techniques of material removal and deposition have been developed. However, it is the pattern of these materials which is critical to the formation of the device and, as integration density has increased, these patterns have become increasingly complex.
The technique of forming material patterns of choice generally involves the use of a resist which may be of the so-called positive or negative type. In general, a resist is a material which is deposited over an area or portion of an area of a layer in which patterning is to be done. The resist material, many of which are known, is sensitive to some type of exposure to radiation, such as light or x-rays, or particles, such as electrons, which can be made to selectively impinge thereon. The exposed areas are thus made differentially removable by further chemical treatment, leaving some portions of one or more underlying layers exposed for selective material removal (e.g. by etching) or deposition (e.g. selective metal deposition).
In the past, such exposures of resists was often done with masks which could be used for multiple exposures for the fabrication of numerous devices. However, as the design rules for integrated circuits have allowed smaller feature sizes for increased integration density, accuracy of registration of discrete masks and other problems has effectively precluded their use in most processes. Instead, it is the present practice for some high density patterns to directly expose the resist with a beam which can be restricted to minute areas and moved across the resist at high speed in a pattern which can be controlled with the required accuracy. An electron beam is well-suited to this purpose and the technology for such systems, often referred to as e-beam tools, which can perform in this manner is well-developed. Also, for the because of high speed and high accuracy available from e-beam tools, they are often the device of choice for the production of masks for exposure of lower density patterns and other structures which require a fine pattern of material to be formed.
However, as mentioned above, the complexity of patterns in integrated circuits of current designs requires extremely large amounts of data to define the patterns. This data must then be transformed into control signals suitable for controlling the e-beam or other controllable beam tool. This task is computationally formidable because of the data volume involved and the generality of shapes which must be accommodated. For example, the design rules for a particular device will, of course, have established parameters for certain categories of connections (e.g. power, signals, clock, etc.) and different predetermined shapes for pads, openings to elements of active devices such as transistors and elements of active devices themselves. Locations of these shapes must be defined during the design of the pattern and overlaps of shapes (including conductors) will occur at many locations. The number of shapes overlapping at a point or within an area is referred to as a cover count. These shapes are then merged into a pattern for the layer by a process called unioning or, simply, union, by virtue of its physical similarity to the logical operation of the same name.
The union operation or procedure essentially removes the overlaps of shapes to find a new set of shapes to define the pattern. This procedure is generally carried out by scanning through the area containing the shapes while looking for edges of shapes and monitoring the cover count. For example, when an edge of a shape is encountered at a particular location in the scan and the area on either side of the edge has a cover count of zero, the portion of the edge at that location will be part of the unioned pattern since it represents a boundary of the composite shape defined by all of the shapes of the pattern design.
As a computational matter, however, it is not practical to define the shapes as points and locations due to the volume of data involved. Instead, it is the practice to define shapes by edges and to define the edges by their end points and another value, commonly an integer, which contains property information, such as orientation (e.g. does the interior of the shape lie above or below the edge or to the right or the left of the edge). Special cases of edges are so-called Cartesian edges which are either horizontal or vertical in the pattern. In many cases also, many non-Cartesian edges will occur at so-called standard angles such as multiples of 45.degree..
A computational complication arises during the unioning procedure since intersections of edges must necessarily be found as the pattern is scanned in strips as part of the unioning process. (A strip is essentially a scan line, in the horizontal direction by convention, which has a vertical address which coincides with the vertical address of a point on at least one edge. The strip has a width which is equal to the interval between addressable locations on the scanned surface. Strips are processed, again by convention, from top to bottom across the pattern). If angled edges are present, the order in which edges will be encountered in each strip will change from strip to strip at each intersection of edges. The determination of edges which must be considered in the unioning process thus requires a search at each addressable point as a strip is scanned in order to determine the edges on which the operation is to be performed. This search operation may potentially require consideration of every edge of every shape in the pattern and, while some simplifying search techniques and data structures, such as balanced trees, have been employed, the search for edges consumes the majority of processing time during execution of the unioning process. This problem of long computation times increases in severity with pattern complexity since a linear increase of search space results in an exponential increase In search time.